Optical recording/reproducing apparatuses require tracking control and focus control with fine light spots on recording media. Actuators, to be specific, linear motors are used for tracking control and focus control. In response to the need for low power consumption in recent years, methods for PWM motor drive achieving high power efficiency have been used for tracking control and focus control.
FIG. 6 shows a conventional apparatus for PWM motor drive.
An actuator 9 is connected between the output of a first output unit 7 and the output of a second output unit 8. The first output unit 7 is made up of a first timing pulse generating section 71 and a first output stage 12. The second output unit 8 is made up of a second timing pulse generating section 81 and a second output stage 22. The first output unit 7 and the second output unit 8 are driven based on a differential input PWM signal from a PWM signal generating section 6. FIG. 7 is a waveform chart showing the inputs/outputs of the parts of FIG. 6.
The PWM signal generating section 6 determines a pulse width according to the level of an analog input signal S50 and generates a differential input PWM signal made up of a first pulse-width modulation (PWM) signal S51 and a second pulse-width modulation (PWM) signal S52.
The first output unit 7 outputs a first output signal S53 in response to the first PWM signal S51. The second output unit 8 outputs a second output signal S54 in response to the second PWM signal S52.
The actuator 9 is driven by the differential component (S53-S54) of the two-phase pulse output signals outputted from the first output unit 7 and the second output unit 8. Also when driving output applied across the actuator 9 is set at zero (hereinafter, will be referred to as zero output), PWM operations are performed by the first PWM signal S51 and the second PWM signal S52.
In other words, when the differential input PWM signal has zero output, the first PWM signal S51 and the second PWM signal S52 are in phase with an equal pulse width.
In the case of output to the actuator 9 in one direction on the average, the “H” level period of the first PWM signal S51 is increased and the “L” level period of the second PWM signal S52 is increased.
In the case of output to the actuator 9 in the other direction on the average, the “L” level period of the first PWM signal S51 is increased and the “H” level period of the second PWM signal S52 is increased.
In other words, in the case of output other than zero output, while the pulse width of the first PWM signal S51 is increased (or reduced), the pulse width of the second PWM signal S52 is reduced (or increased).
To be specific, when the first output signal S53 outputted from the first output unit 7 and the second output signal S54 outputted from the second output unit 8 are in phase with an equal pulse width as indicated on time A of FIG. 7, the actuator 9 is not driven (zero output). In the case of a large difference in duty ratio as indicated on times B and C of FIG. 7, the actuator 9 is driven by a large signal biased in either of the directions.
FIG. 8 shows the specific circuit configurations of the first and second output units 7 and 8.
The first timing pulse generating section 71 of the first output unit 7 is made up of a delay circuit 72, a NAND gate 73, and a NOR gate 74. The first output stage 12 is made up of a pair of transistors 121 and 122. The transistor 121 is a P-type FET and the transistor 122 is an N-type FET.
The second timing pulse generating section 81 of the second output unit 8 is made up of a delay circuit 82, a NAND gate 83, and a NOR gate 84. The second output stage 22 is made up of a pair of transistors 221 and 222.
In the first and second output stages 12 and 22, the sources of the transistors 121 and 221 are connected to one pole 3 of a power supply and the sources of the transistors 122 and 222 are connected to ground 5 which is the other pole of the power supply, so that a bridge circuit is formed. The actuator 9 is connected between a node 31 of the drain of the transistor 121 and the drain of the transistor 122 and a node 32 of the drain of the transistor 221 and the drain of the transistor 222. The series circuit of the transistors 121 and 122 and the series circuit of the transistors 221 and 222 are each called a half-bridge circuit.
The first and second output units 7 and 8 are identical in circuit configuration and the actuator 9 is driven by the differential component (S53-S54) of the two pulses, so that even when the output pulses of the first output unit 7 and the second output unit 8 mostly cancel each other out, a load is driven by a differential output which is operated according to a level difference and a time difference between the output pulses of the first output unit 7 and the second output unit 8. FIG. 9 shows an output current effective value relative to a time difference between the first PWM signal S51 and the second PWM signal S52. As the time difference comes close to zero, a dead zone appears with no response of the output current effective value. The horizontal axis of FIG. 9 represents a time difference between the first PWM signal S51 and the second PWM signal S52 and the vertical axis of FIG. 9 represents an output current effective value.
Such a conventional configuration is disclosed in Japanese Patent Publication No. 7-117841.